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P036F048T12AL
PRM PRMTM
Regulator
* 36 V input V*I ChipTM PRM * Vin range 18 - 60 Vdc * High density - 407 W/in3 * Small footprint - 1.1 in2 * Low weight - 0.5 oz (15 g) * Adaptive Loop feedback * ZVS buck-boost regulator * 1.35 MHz switching frequency * 95% Efficiency * 125C operation (Tj) Vin = 18 - 60 Vdc Vf = 26 - 55 Vdc Pf = 120 W If = 2.5 A
(c)
Product Description
The V*I Chip Pre-Regulator Module is a very efficient non-isolated regulator capable of both boosting and bucking a wide range input voltage. It is specifically designed to provide a controlled Factorized Bus distribution voltage for powering downstream V*I Chip Voltage Transformation Modules -- fast, efficient, isolated, low noise Point-of-Load (POL) converters. In combination, PRMs and VTMsTM form a complete DC-DC converter subsystem offering all of the unique benefits of Vicor's Factorized Power Architecture (FPA): high density and efficiency; low noise operation; architectural flexibility; extremely fast transient response; and elimination of bulk capacitance at the Point-of-Load (POL). In FPA systems, the POL voltage is the product of the Factorized Bus voltage delivered by the PRM and the "K-factor" (the fixed voltage transformation ratio) of a downstream VTM. The PRM controls the Factorized Bus voltage to provide regulation at the POL. Because VTMs perform true voltage division and current multiplication, the Factorized Bus voltage may be set to a value that is substantially higher than the bus voltages typically found in "intermediate bus" systems, reducing distribution losses and enabling use of narrower distribution bus traces. A PRM-VTM chip set can provide up to 100 A, or 115 W at a FPA system density of 169 A/in3, or 195 W/in3 -- and because the PRM can be located, or "factorized," remotely from the POL, these power densities can be effectively doubled. The PRM described in this data sheet features a unique "Adaptive Loop" compensation feedback: a single wire alternative to traditional remote sensing and feedback loops that enables precise control of an isolated POL voltage without the need for either a direct connection to the load or for noise sensitive, bandwidth limiting, isolation devices in the feedback path.
Absolute Maximum Ratings
Parameter
+In to -In PC to -In PR to -In IL to -In VC to -In +Out to -Out SC to -Out VH to -Out OS to -Out CD to -Out SG to -Out Continuous output current Continuous output power Case temperature during reflow Operating junction temperature Storage temperature
Values
-1.0 to 85.0 -0.3 to 6.0 -0.3 to 9.0 -0.3 to 6.0 -0.3 to 18.0 -0.3 to 59 -0.3 to 3.0 -0.3 to 9.5 -0.3 to 9.0 -0.3 to 9.0 100 2.5 120 225 -40 to 125 -40 to 125
Unit
Vdc Vdc Vdc Vdc Vdc Vdc Vdc Vdc Vdc Vdc mA Adc W C C C
Notes
MSL 5 T-Grade T-Grade
DC-DC Converter
VC PC TM IL NC PR VH SC SG OS NC CD
+In
PRM-AL
Factorized Bus (Vf)
+In
+Out
+Out
TM VC PC
VTM K Ro
-Out
Vout
+Out
Vin
-In -Out -In
-Out
The P036F048T12AL is used with any 048 input series VTM to provide a regulated and isolated output.
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V*I Chip Pre-Regulator Module
P036F048T12AL
Rev. 1.5
Page 1 of 14
General Specifications Part Numbering
V*I Chip Pre-Regulator Module
P
Pre-Regulator Module
036
Input Voltage Designator
F
Configuration F = J-lead T = Through hole
048
Nominal Factorized Bus Voltage
T
Product Grade Temperatures (C) Grade Storage Operating (TJ) T -40 to125 -40 to125
12
Output Power Designator (=Pf /10)
AL
AL = Adaptive Loop
Overview of Adaptive Loop Compensation Adaptive Loop compensation, illustrated in Figure 1, contributes to the bandwidth and speed advantage of Factorized Power. The PRM monitors its output current and automatically adjusts its output voltage to compensate for the voltage drop in the output resistance of the VTM. ROS sets the desired value of the VTM output voltage, Vout; RCD is set to a value that compensates for the output resistance of the VTM (which, ideally, is located at the point of load). For selection of ROS and RCD, refer to Table 1 below or Page 9. The V*I Chip's bi-directional VC port : 1. Provides a wake up signal from the PRM to the VTM that synchronizes the rise of the VTM output voltage to that of the PRM. 2. Provides feedback from the VTM to the PRM to enable the PRM to compensate for the voltage drop in VTM output resistance, RO.
Vo = VL 1.0%
VC PC TM IL NC PR VH SC SG OS NC CD
ROS RCD
+In
PRM-AL
Factorized Bus (Vf)
Vf = VL (Io*Ro) + K K
+In
+Out
+Out
TM VC PC
VTM K Ro
-Out
+Out
Vin
-In -Out
-In
L O A D
-Out
Figure 1 -- With Adaptive Loop control, the output of the VTM is regulated over the load current range with only a single interconnect between the PRM and VTM and without the need for isolation in the feedback path.
Desired Load Voltage (Vdc) 1.0 1.2 1.5 1.8 2.0 3.0 3.3 5.0 8.0 9.6 10 12 15 24 28 36 48
VTM P/N(1) V048F015T100 V048F015T100 V048F015T100 V048F020T080 V048F020T080 V048F030T070 V048F040T050 V048F060T040 V048F080T030 V048F096T025 V048F120T025 V048F120T025 V048F160T015 V048F240T012 V048F320T009 V048F480T006 V048F480T006
Max VTM Output Current (A)(2) 100 100 100 80 80 70 50 40 30 25 25 25 15 12.5 9.4 6.3 6.3
ROS (k)(3) 3.57 2.94 2.37 2.61 2.37 2.37 2.89 2.87 2.37 2.37 2.86 2.37 2.49 2.37 2.74 3.16 2.37
RCD ()(3) 26.1 32.4 39.2 35.7 39.2 39.2 32.6 33.2 32.9 32.9 32.9 39.2 37.4 39.2 35.7 30.1 39.2
Note: (1) See Table 2 on page 9 for nominal Vout range and K factors. (2) See "PRM output power vs. VTM output power" on Page 10 (3) 1% precision resistors recommended Table 1 -- Configure your Chip Set using the PRM-AL
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Electrical Specifications Input Specs (Conditions are at 36 Vin, 48 Vf, full load, and 25C ambient unless otherwise specified)
Parameter Input voltage range Input dV/dt Input undervoltage turn-on Input undervoltage turn-off Input overvoltage turn-on Input overvoltage turn-off Input quiescent current Input current Input reflected ripple current No load power dissipation Internal input capacitance Recommended external input capacitance 15.2 60 17 15.9 62 63 0.5 3.5 586 3 5 100 6 65 1 Min 18 Typ 36 Max 60 1 17.6 Unit Vdc V/s Vdc Vdc Vdc Vdc mA Adc mA p-p W F F Ceramic PC low Note
V*I Chip Pre-Regulator Module
See Figures 4 & 5
See Figure 5 for input filter circuit. Source impedance dependent
Input Waveforms
Figure 2 -- Vf and PC response from power up
Figure 3 -- Vf turn-on waveform with inrush current - PC enabled
Reflected Ripple Measurement
VC PC TM IL NC PR
10 A
+IN
100 F Al-Electrolytic
+In
PRM-AL
VH SC SG OS NC CD
2.37 k
+Out
+ OUT
-IN
-In
-Out
- OUT
Figure 4 -- Input reflected ripple current
Figure 5 -- Input filter capacitor recommendation
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Electrical Specifications (continued) Output Specs (Conditions are at 36 Vin, 48 Vf, full load, and 25C ambient unless otherwise specified)
Parameter Output voltage range Output power Output current DC current limit Average short circuit current Set point accuracy Line regulation Load regulation Load regulation (at VTM output) Current share accuracy Efficiency Full load Output overvoltage set point Output ripple voltage No external bypass With 10 F capacitor Switching frequency Output turn-on delay From application of power From PC pin high Internal output capacitance Factorized Bus capacitance 74 100 5 47 250 ms s F F 1.26 1.51 0.42 1.35 3.5 1.0 1.46 % % MHz 56 95 59.4 % Vdc 1.5 0.1 0.1 1.0 5 0.2 0.2 2.0 10 Min 26 0 0 2.6 2.96 Typ 48 Max 55 120 2.5 3.3 1.25 Unit Vdc W Adc Adc A % % % % % Note
V*I Chip Pre-Regulator Module
Factorized Bus voltage (Vf) set by ROS
IL pin floating Auto recovery Low line to high line No CD resistor Adaptive Loop See description page 8 See Figure 6,7 & 8
Factorized Bus, see Figure 13 Factorized Bus, see Figure 14 Fixed frequency See Figure 2 See Figure 3 Ceramic
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Electrical Specifications (continued) Efficiency Graphs
Efficiency vs. Output Current
100 95
Vin 18 V 36 V 60 V
V*I Chip Pre-Regulator Module
Efficiency vs. Output Current
100 95
Vin 18 V 36 V 60 V
Efficiency (%)
90 85 80 75.
Efficiency (%)
90 85 80 75 70 65
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
Output Current (A) Figure 6 -- Efficiency vs. output current at 48 Vf
Output Current (A) Figure 7 -- Efficiency vs. output current at 36 Vf
Efficiency vs. Output Current
100 95
Vin 18 V 36 V 60 V
Efficiency (%)
90 85 80 75 70 65
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
Output Current (A) Figure 8 -- Efficiency vs. output current at 26 Vf
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Electrical Specifications (continued)
V*I Chip Pre-Regulator Module
Figure 9 -- Transient response; PRM alone 36 Vin, 0 - 2.5 - 0 A no load capacitance, local loop and 48 Vf
Figure 10 -- Transient response; PRM alone 18 Vin, 0 - 2.5 - 0 A no load capacitance, local loop and 48 Vf
Figure 11 -- Transient response; PRM alone 60 Vin, 0 - 2.5 - 0 A no load capacitance, local loop and 48 Vf
Figure 12 -- PC during fault - frequency will vary as a function of line voltage
Figure 13 -- Output ripple full load no bypass capacitance. Vf = 48 Vdc
Figure 14 -- Output ripple full load 10F bypass capacitance. Vf = 48 Vdc
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Electrical Specifications (continued) Auxiliary Pins (Conditions are at 36 Vin, 48 Vf, full load, and 25C ambient unless otherwise specified)
Parameter VC (VTM Control) Pulse width Peak voltage PC (Primary Control) DC voltage Module disable voltage Module enable voltage Disable hysteresis Current limit Enable delay time Disable delay time IL (Current Limit Adjust) Voltage Accuracy PR (Parallel Port) Voltage Source current External capacitance VH (Auxiliary Voltage) Range Regulation Current SC (Secondary Control) Voltage Internal capacitance External capacitance OS (Output Set) Set point accuracy Reference offset CD (Compensation Device) External resistance Min 8 12 4.8 2.3 Typ 12 14 5.0 2.4 2.5 100 1.75 100 1 1 15 0.5 1 3.5 100 8.7 9.0 0.04 9.3 5 1.23 1.24 0.22 1.25 0.7 1.5 4 20 Max 18 18 5.2 2.6 Unit ms V Vdc Vdc Vdc mV mA s s V % V mA pF Vdc %/mA mA p Vdc F F % mV Note
V*I Chip Pre-Regulator Module
Referenced to -Out Referenced to -In Referenced to -In
1.90
Source only after start up; not to be used for aux. supply; 100 k minimum load impedance to assure start up.
Based on DC current limit set point Referenced to SG; See description page 8
Typical internal bypass C= 0.1 F Maximum external C=0.1 F, referenced to SG See description page 8 Referenced to SG
Includes 1% external resistor
Omit resistor for regulation at output of PRM
General Specs
Parameter MTBF MIL-HDBK-217F Agency approvals (pending) Mechanical parameters Weight Dimensions Length Width Height Min Typ 2.2 cTUVus CE Mark 0.5 3/ 15 1.28 / 32,5 0.87 / 22,0 0.26 5/ 6,73 135 9.3 1.1 2.1 3.7 140 Max Unit Mhrs Note 25C, GB UL/CSA 60950-1, EN60950-1 Low voltage directive See Mechanical Drawings, Figures 19 - 22
oz / g in / mm in / mm in / mm C Ws/C C/W C/W C/W
Thermal
Over temperature shutdown 125 Thermal capacity Junction-to-case thermal impedance (RJC) Junction-to-board thermal impedance (RJB) Case-to-ambient Junction temperature
With 0.25" heat sink @ 300 LFM
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Page 7 of 14
Pin / Control Functions
+In / -In DC Voltage Ports The V*I Chip maximum input voltage should not be exceeded. PRMs have internal over / undervoltage lockout functions that prevent operation outside of the specified input range. PRMs will turn on when the input voltage rises above its undervoltage lockout. If the input voltage exceeds the overvoltage lockout, PRMs will shut down until the overvoltage fault clears. PC will toggle indicating an out of bounds condition. +Out / -Out Factorized Voltage Output Ports These ports provide the Factorized Bus voltage output. The -Out port is connected internally to the -In port through a current sense resistor. The PRM has a maximum power and a maximum current rating and is protected if either rating is exceeded. Do not short -Out to -In. VC - VTM Control The VTM Control (VC) port supplies an initial VCC voltage to downstream VTMs, enabling the VTMs and synchronizing the rise of the VTM output voltage to that of the PRM. The VC port also provides feedback to the PRM to compensate for voltage drop due to the VTM output resistance. The PRM's VC port should be connected to the VTM VC port. A PRM VC port can drive a maximum of two (2) VTM VC ports. PC - Primary Control The PRM voltage output is enabled when the PC pin is open circuit (floating). To disable the PRM output voltage, the PC pin is pulled low. Open collector optocouplers, transistors, or relays can be used to control the PC pin. When using multiple PRMs in a high power array, the PC ports should be tied together to synchronize their turn on. During an abnormal condition the PC pin will pulse (Fig.12) as the PRM initiates a restart cycle. This will continue until the abnormal condition is rectified. The PC should not be used as an auxiliary voltage supply, nor should it be switched at a rate greater than 1 Hz. TM - Factory Use Only IL - Current Limit Adjust The PRM has a preset, maximum, current limit set point. The IL port may be used to reduce the current limit set point to a lower value. See "adjusting current limit" on page 10. PR - Parallel Port The PR port signal, which is proportional to the PRM output power, supports current sharing of two PRMs. To enable current sharing, PR ports should be interconnected. Bypass capacitance should be used when interconnecting PR ports and steps should be taken to minimize coupling noise into the interconnecting bus. Terminate this port with a 10 k equivalent resistance to SG, e.g. 10 k for a single PRM, 20 k each for 2 PRMs in parallel, 30 k each for 3 PRMs in parallel etc.. Please consult Vicor Applications Engineering regarding additional considerations when paralleling more than two PRMs. VH - Auxiliary Voltage VH is a gated (e.g. mirrors PC), non-isolated, nominally 9 Volt, regulated DC voltage (see "Auxiliary Pins" specifications, on Page 7) that is referenced to SG. VH may be used to power external circuitry having a total current consumption of no more than 5 mA under either transient or steady state conditions including turn-on. vicorpower.com 800-735-6200
AL Version
4 3
V*I Chip Pre-Regulator Module
2
1 A B C D E F
VH SC SG OS NC CD
A B C D E F
VC PC TM IL NC PR
G
G H J K
+OUT
H J K
+IN
L
L M N P
-OUT
M N P
-IN
Bottom View
Signal Name +In -In VC PC TM IL PR VH SC SG OS CD +Out -Out
Designation G1-K1,G2-K2 L1-P1, L2-P2 A1,A2 B1, B2 C1, C2 D1, D2 F1, F2 A3, A4 B3, B4 C3, C4 D3, D4 F3, F4 G3-K3, G4-K4 L3-P3, L4-P4
Figure 15 -- PRM pin configuration
SC - Secondary Control The load voltage may be controlled by connecting a resistor or voltage source to the SC port. The slew rate of the output voltage may be controlled by controlling the rate-of-rise of the voltage at the SC port (e.g., to limit inrush current into a capacitive load). SG - Signal Ground This port provides a low inductance Kelvin connection to -In and should be used as reference for the OS, CD, SC,VH and IL ports. OS - Output Set The application-specific value of the Factorized Bus voltage (Vf) is set by connecting a resistor between OS and SG. Resistor value selection is shown in Table 1 on Page 2, and described on Page 9. If no resistor is connected, the PRM output will be approximately one volt. If set resistor is not collocated with the PRM a load bypass capacitor of ~200 pF may be required. CD - Compensation Device Adaptive Loop control is configured by connecting an external resistor between the CD port and SG. Selection of an appropriate resistor value (see Equation 2 on Page 9 and Table 1 on Page 2) configures the PRM to compensate for voltage drops in the equivalent output resistance of the VTM and the PRM-VTM distribution bus. If no resistor is connected to CD, the PRM will be in Local Loop mode and will regulate the +Out / -Out voltage to a fixed value.
V*I Chip Pre-Regulator Module
P036F048T12AL
Rev. 1.5
Page 8 of 14
Application Information
V*I Chip Pre-Regulator Module
0.01 F
VC PC TM IL NC PR
10 k
+In
PRM-AL
VH SC SG OS NC CD
Vf =
ROS RCD
(IL*Ro) VL + K K
+In
+Out
+Out
0.4 H
TM VC PC
VTM
+Out
- Out
Vin
-In -Out
10
- In
K Ro - Out
L O A D
Figure 16 -- Adaptive Loop compensation with soft start using the SC port.
Output Voltage Setting with Adaptive Loop The equations for calculating ROS and RCD to set a VTM output voltage are: 93100 ROS = ( VL * 0.8395 ) - 1 K (1)
Output Voltage Trimming (optional) After setting the output voltage from the procedure above the output may be margined down (26 Vf min) by a resistor from SC-SG using this formula: Rd = 10000 Vfd Vfs - Vfd
RCD =
91238 ROS
+1
(2)
Where Vfd is the desired factorized bus and Vfs is the set factorized bus. A low voltage source can be applied to the SC port to margin the load voltage in proportion to the SC reference voltage. An external capacitor can be added to the SC port as shown in Figure 16 to control the output voltage slew rate for soft start.
VL = Desired load voltage VOUT = VTM output voltage K = VTM transformation ratio (available from appropriate VTM data sheet) Vf = PRM output voltage, the Factorized Bus (see Figure 16) RO = VTM output resistance (available from appropriate VTM data sheet) IL = Load Current (actual current delivered to the load)
Nominal Vout Range (Vdc) 0.8 1.1 1.6 2.2 3.3 4.3 6.5 8.7 13.0 17.4 26.0 1.6 2.2 3.3 4.4 6.6 8.8 13.4 17.9 26.9 36.0 54.0
VTM K Factor 1/32 1/24 1/16 1/12 1/8 1/6 1/4 1/3 1/2 2/3 1
Table 2 -- 048 input series VTM K factor selection guide
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Application Information (continued)
OVP - Overvoltage Protection The output overvoltage protection set point of the P036F048T12AL is factory preset for 56 V. If this threshold is exceeded the output shuts down and a restart sequence is initiated, also indicated by PC pulsing. If the condition that causes OVP is still present, the unit will again shut down. This cycle will be repeated until the fault condition is removed. The OVP set point may be set at the factory to meet unique high voltage requirements. PRM Output Power Versus VTM Output Power As shown in Figure 17, the P036F048T12AL is rated to deliver 2.5 A maximum, when it is delivering an output voltage in the range from 26 V to 48 V, and 120 W, maximum, when delivering an output voltage in the range from 48 V to 55 V. When configuring a PRM for use with a specific VTM, refer to the appropriate VTM data sheet. The VTM input power can be calculated by dividing the VTM output power by the VTM efficiency (available from the VTM data sheet). The input power required by the VTM should not exceed the output power rating of the PRM.
Resistance (k)
V*I Chip Pre-Regulator Module
Adjusting Current Limit The current limit can be lowered by placing an external resistor between the IL and SG ports (see Figure 18 for resistor values). With the IL port open-circuit, the current limit is preset to be within the range specified in the output specifications table on Page 4.
100
10
1 0 0.5 1 1.5 2 2.5 3
Desired PRM Output Current Limit (A)
2.55 2.50 2.45
Figure 18 -- Calculated external resistor value for adjusting current limit, actual value may vary.
Current (A)
2.40 2.35 2.30 2.25 2.20 2.15
Input Fuse Recommendations
Safe Operating Area
0
~ ~
20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
A fuse should be incorporated at the input to the PRM, in series with the +IN port. A fast acting fuse, NANO2 FUSE 451/453 Series 10 A 125 V, or equivalent, may be required to meet certain safety agency Conditions of Acceptability. Always ascertain and observe the safety, regulatory, or other agency specifications that apply to your specific application. Product Safety Considerations If the input of the PRM is connected to SELV or ELV circuits, the output of the PRM can be considered SELV or ELV respectively. If the input of the PRM is connected to a centralized DC power system where the working or float voltage is above SELV, but less than or equal to 75 V, the input and output voltage of the PRM should be classified as a TNV-2 circuit and spaced 1.3 mm from SELV circuitry or accessible conductive parts according to the requirements of UL60950-1, CSA 22.2 60950-1, EN60950-1, and IEC60950-1.
Factorized Bus Voltage (Vf)
Figure 17 -- P036F048T12AL rating based on Factorized Bus voltage
The Factorized Bus voltage should not exceed an absolute limit of 55 V, including steady state, ripple and transient conditions. Exceeding this limit may cause the internal OVP set point to be exceeded. Parallel Considerations The PR port is used to connect two PRMs in parallel to form a higher power array. When configuring arrays, PR port interconnection terminating impedance is 10 k to SG. See note Page 8 and refer to Application Note AN002. Additionally one PRM should be designated as the master while all other PRMs are set as slaves by shorting their SC pin to SG. The PC pins must be directly connected (no diodes) to assure a uniform start up sequence. Consult Vicor applications engineering for applications requiring more than two PRMs.
Application Notes For PRM and V*I Chip application notes on soldering, board layout, and system design please click on the link below: http://www.vicorpower.com/technical_library/application_information/chips/ Applications Assistance Please contact Vicor Applications Engineering for assistance, 1-800-927-9474, or email at apps@vicorpower.com.
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V*I Chip Pre-Regulator Module
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Page 10 of 14
Mechanical Drawings
V*I Chip Pre-Regulator Module
NOTES: mm 1. DIMENSIONS ARE inch . 2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005] 3. PRODUCT MARKING ON TOP SURFACE DXF and PDF files are available on vicorpower.com
Figure 19 -- PRM J-Lead mechanical outline; Onboard mounting
RECOMMENDED LAND PATTERN ( COMPONENT SIDE SHOWN )
NOTES: mm 1. DIMENSIONS ARE inch . 2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005] 3. PRODUCT MARKING ON TOP SURFACE DXF and PDF files are available on vicorpower.com
Figure 20 -- PRM J-Lead PCB land layout information; Onboard mounting
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Mechanical Drawings (continued)
V*I Chip Pre-Regulator Module
NOTES: (mm) 1. DIMENSIONS ARE inch . 2. UNLESS OTHERWISE SPECIFIED TOLERANCES ARE: X.X [X.XX] = 0.25 [0.01]; X.XX [X.XXX] = 0.13 [0.005] 3. RoHS COMPLIANT PER CST-0001 LATEST REVISION DXF and PDF files are available on vicorpower.com
Figure 21 -- PRM Through-hole mechanical outline
NOTES: (mm) 1. DIMENSIONS ARE inch . 2. UNLESS OTHERWISE SPECIFIED TOLERANCES ARE: X.X [X.XX] = 0.25 [0.01]; X.XX [X.XXX] = 0.13 [0.005] 3. RoHS COMPLIANT PER CST-0001 LATEST REVISION DXF and PDF files are available on vicorpower.com
Figure 22 -- PRM Through-hole PCB layout information
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Configuration Options
V*I Chip Pre-Regulator Module
NOTES: 1. MAINTAIN 3.5/[0.138] DIA. KEEP OUT ZONE FREE OF COPPER. ALL PCB LAYERS. 2. MINIMUM RECOMMENDED PITCH IS 39.50/[1.555]. THIS PROVIDES 7.00/[0.276] COMPONENT EDGE-TO-EDGE SPACING. AND 0.50/[0.020] CLEARANCE BETWEEN VICOR HEAT SINKS. 3. V*I CHIP LAND PATTERN SHOWN FOR REFERENCE ONLY; ACTUAL LAND PATTERN MAY DIFFER. DIMENSIONS FROM EDGES OF LAND PATTERN TO PUSH-PIN HOLES WILL BE THE SAME FOR ALL FULL SIZE V*I CHIPS. (mm) 4. DIMENSION ARE inch .
2.950.07 o (2) PL [0.1160.003] NON-PLATED THROUGH HOLE SEE NOTE 1.
(36.50) 1.437 (18.25) 0.719 DOTTED LINE INDICATES VIC POSITION SEE NOTE 3
(4.37) 0.172 (11.37) 0.448
(7.00) 0.276
(2.510) 0.099
(31.48) 1.240
(39.50) 1.555 SEE NOTE 2.
HEAT SINK PUSH-PIN HOLE PATTERN ( TOP SIDE SHOWN )
SEE NOTE 3
Figure 23 -- Hole location for push pin heat sink relative to V*I Chip
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Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to the original purchaser only. EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Vicor will repair or replace defective products in accordance with its own best judgement. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies Vicor against all damages.
Vicor's comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor's Terms and Conditions of Sale, which are available upon request.
Specifications are subject to change without notice.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products described in this data sheet. Interested parties should contact Vicor's Intellectual Property Department. The products described on this data sheet are protected by the following U.S. Patents Numbers: 5,945,130; 6,403,009; 6,710,257; 6,788,033; 6,940,013; 6,969,909; 7,038,917; 7,154,250; 7,166,898; 7,187,263; 7,202,646; 7,361,844; 7,368,957; RE40,072; D496,906; D506,438; D509,472; and for use under 6,975,098 and 6,984,965
Vicor Corporation 25 Frontage Road Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 email Customer Service: custserv@vicorpower.com Technical Support: apps@vicorpower.com
vicorpower.com
800-735-6200
V*I Chip Pre-Regulator Module
P036F048T12AL
Rev. 1.5
9/09

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